Position: ASIC Physical Design Engineer
Location: Warsaw, Poland
Employment Type: Full-time Employment Contract (UoP)
Salary: Up to 29,000 PLN gross / month
About the Project
At Ideamotive, we are conducting a recruitment process for a Polish deep-tech company. Our client develops hardware post-quantum cryptography accelerators in silicon, designed to withstand attacks from future quantum computers. We are looking for an experienced engineer to take full ownership of the physical design domain and drive it from floorplanning to sign-off. You will join an already established team of experts where your specific expertise is the missing key piece.
Key Responsibilities
Leading the full physical implementation flow for quantum-resistant cryptographic processors.
Executing floorplanning, placement, clock tree synthesis (CTS), and routing.
Managing timing closure and STA sign-off across multiple corners and modes.
Taking ownership of power planning, IR-drop analysis, and electromigration checks.
Designing low-power architectures, including power domains, level shifters, isolation cells, and body bias distribution networks for Adaptive Body Bias (ABB).
Performing handoff to layout, implementing ECOs, and preparing for tape-out in direct collaboration with the foundry.
Creating technical documentation and supporting the chip certification process.
Requirements
EU Citizenship (strict formal requirement).
Minimum 5 years of commercial experience in ASIC back-end / physical design.
Proven track record of independently owning at least one tape-out from floorplan to sign-off.
Hands-on proficiency with Place & Route tools: Cadence Innovus or Synopsys IC Compiler II / Fusion Compiler.
Practical experience with STA analysis and sign-off using Synopsys PrimeTime or Cadence Tempus.
Familiarity with physical verification tools (DRC/LVS) such as Siemens Calibre, Synopsys IC Validator, or Cadence Pegasus.
Experience with low-power design methodologies and UPF or CPF standards.
Solid understanding of the full ASIC design flow and the front-end to back-end interface.
Degree in Electronics, Computer Engineering, or a related technical field.
Nice to Have
Experience with FD-SOI technology, specifically GlobalFoundries 22FDX.
Hands-on practice implementing Adaptive Body Bias (ABB).
Demonstrated success in power consumption optimization.
Knowledge of hardware security concepts: TRNG, PUF, and side-channel attack countermeasures.
Active security clearance (National, EU, or NATO).
What We Offer
Employment strictly based on a Polish Employment Contract (UoP).
Application of 50% Tax-Deductible Costs (KUP) for creative/R&D work, significantly increasing net income.
Employee Stock Option Plan (ESOP) for key engineering staff, launched upon conversion into a Joint-Stock Company.
Stable employment in a project with guaranteed multi-year funding.
Opportunity to work on a unique, cutting-edge post-quantum cryptography technology within Europe.